This invention relates to a delay locked loop, a synchronizing method for the delay locked loop and a semiconductor device equipped with the delay locked loop. Particularly, this invention relates to a delay locked loop that allows an internal clock, which is obtained delaying an external clock supplied from outside by a given delay time, to be synchronized with the external clock.
One of typical methods of operating a large-scale and complex digital circuit with good stability and efficiency is synchronous circuit designing that allows all logic cells (flip flop (FF), latch etc.) in the digital circuit to operate synchronizing with one clock. Semiconductor devices such as large-scale integrated circuit (LSI), very-large-scale integrated circuit (VLSI) and ultra-large-scale integrated circuit also have one digital circuit formed on the chip, and they are designed mostly by the synchronous circuit designing.
In order to lead a digital circuit designed by such synchronous circuit designing to accurate operation, all logic cells need to operate at the same timing. This is because, if there is a gap between clocks that are input to the respective logic cells, a problem described below occurs. For example, when multiple FFs cascade-connected compose a shift register, if the rise or fall of clock input to a subsequent FF slightly gets behind the rise or fall of clock input to the previous FF, the output data of the previous FF changes in the instant that the subsequent FF is going to take the output data of the previous FF. Therefore, the subsequent FF may incur a malfunction, for example, data that is due to delay by one cycle maybe, without delay, output from the subsequent FF. Such a phenomenon is called racing.
Also in synchronous semiconductor storage, responding to data reading command to be sent from CPU, data is read synchronizing with an internal clock that is generated synchronizing with an external clock supplied from outside. However, if out of synchronization, the PCU fails to accurately read data, therefore the CPU and the entire system will be subjected to a malfunction.
In recent years, the number of logic cells composing a semiconductor device increases as the integration density and operation speed of a semiconductor device such as LSI increases. When a digital circuit is formed on chip of such a semiconductor device, the number of logic cells to operate simultaneously increases. Therefore, the risk of occurrence of the above-mentioned racing and an error in data reading becomes high.
Because of this, recently, produced are semiconductor devices that a phase-adjusting circuit such as phase locked loop (PLL) or delay locked loop (DLL) is installed so that a clock supplied to all logic cells is synchronized with an external clock supplied from outside or an internally-generated clock supplied from an internal clock generating means.
PLL is, for example, composed of a phase comparison circuit, a low-pass filter (LPF) and a voltage-controlled oscillator (VCO). The phase comparison circuit compares a phase of the external clock or internally-generated clock with a phase of internal clock supplied from the VCO, and outputs a phase error signal according to its phase error. The LPF smoothes the phase error signal, and outputs it as control voltage. The VCO oscillates at an internal clock based on the control voltage, and supplies the internal clock to the phase comparison circuit.
DLL is, for example, composed of a phase comparison circuit, a delay circuit and an LPF. The phase comparison circuit compares a phase of the external clock or internally-generated clock with a phase of internal clock supplied from the VCO, and outputs a phase error signal according to its phase error. The LPF smoothes the phase error signal, and outputs it as control voltage. The delay circuit makes the external clock or internally-generated clock delay based on the control voltage, and supplies it as an internal clock to the phase comparison circuit.
Since, of these phase-adjusting circuits, the DLL is not equipped with especially the VCO as installed in the PLL, the DLL allows the phase adjusting circuit to be composed with fewer number of elements and low power consumption.
FIG. 1 is a block diagram showing an example of partial composition of semiconductor device equipped with a conventional DLL.
In this example, the semiconductor device is composed of a phase comparison circuit 1, a counter 2, a digital-to-analogue converter (DAC) 3, a delay circuit 4, flip flops (FF) 5 and 6, buffers and 8, and an output dummy circuit 9.
The phase comparison circuit 1 compares a phase of external lock ECK supplied from outside with a phase of dummy data DDT supplied from the output dummy circuit 9. When the phase of external clock ECK is behind the phase of dummy data DDT, the phase comparison circuit 1 outputs an up clock UCK with pulses of number according to the phase difference, to the counter 2. When the phase of external clock ECK is ahead of the phase of dummy data DDT, the phase comparison circuit 1 outputs a down clock DCK with pulses of number according to the phase difference, to the counter 2.
The counter 2 outputs a count value CT to be counted up or counted down according to the up clock UCK or down clock DCK supplied from the phase comparison circuit 1, to the DAC 3.
The DAC 3 converts the count value CT supplied from the counter 2 into analogue delay voltage VD, and supplies it to the delay circuit 4.
The delay circuit 4 allows the delay time to be changed according to the delay voltage VD supplied from the DAC 3, and delays the external clock ECK by that delay time, then outputting it as an internal clock ICK. The range of the delay time changed in the delay circuit 4 is set to be at least one cycle of the external clock ECK. For example, when the frequency of the external clock ECK is 100 MHz, the range of changing is set to be 0 to 10 ns.
FIG.2 shows an example of composition of the delay circuit 4. The delay circuit 4 is composed of inverters 11 to 14, N-channel FETs 15 to 17 and capacitors 18 to 20. The inverters 11 to 14 are cascade-connected, and the external clock ECK is applied to the input of the inverter 11 and the internal clock ICK is output from the output of the inverter 14. The respective gates of the FETs 15 to 17 are connected each other, and delay voltage VD is applied to the gates. The FET 15 has the source connected to the connection point between the output of the inverter 11 and the input of the inverter 12, and has the drain connected to one end of the capacitor 18, the other end of the capacitor 18 being grounded. Similarly, the FET 16 has the source connected to the connection point between the output of the inverter 12 and the input of the inverter 13, and has the drain connected to one end of the capacitor 19, the other end of the capacitor 19 being grounded. The FET 17 has the source connected to the connection point between the output of the inverter 13 and the input of the inverter 14, and has the drain connected to one end of the capacitor 20, the other end of the capacitor 20 being grounded.
Since the delay time of the delay circuit 4 cannot be shorter than the sum of the delay times of the four inverters 11 to 14, if the phase of external clock ECK is ahead of the phase of dummy data DDT, by delaying the phase of internal clock ICK by amount of phase obtained subtracting the phase being advanced from the phase of one cycle, the phase of external clock ECK is made to coincide with the phase of dummy data DDT, i.e., the phase of internal clock ICK. For example, when the frequency of external clock ECK is 100 MHz, one cycle is 10 ns. Given that the sum of the delay times of the four inverters 11 to 14 is, for example, 5 ns, when the count number CT of the counter 2 is five and the delay voltage is 0.5 V, the delay time of the delay circuit 4 is further increased by 5 ns, thereby being 10 ns totally. In this way, the phase of external clock ECK is made to coincide with the phase of dummy data DDT.
In FIG. 1, the FFs 5 and 6 hold and output data to be supplied from a circuit element (not shown) in the semiconductor device synchronizing with the rise of internal clock ICK supplied from its clock input C, and supply them to the buffers 7 and 8. The buffers 7 and 8 buffer the data supplied from the FFs 5 and 6, respectively, and output them as data DT1 and DT2 from the output terminals. The FF 5 and the buffer 7, and the FF 6 and the buffer 8 compose the output circuit of the data DT1 and DT2, respectively. The output dummy circuit 9 corresponds to the pseudo-composition of FF, buffer or capacitance of load connected to the output terminal that compose the output circuit, and outputs dummy data DDT being synchronized with the rise of internal clock ICK to the phase comparison circuit 1. The delay time TDD Of the output dummy circuit 9 is set to be delay time TD obtained summing the delay time of the FF 5 and the buffer 7 with a given load added.
The phase comparison circuit 1, the counter 2, the DAC 3, the delay circuit 4 and the output dummy circuit 9 compose the DLL.
The partial operation of the semiconductor device thus composed is explained below.
First, given that the frequency of external clock ECK is 100 MHz, for example, when the phase of external clock ECK is slightly behind the phase of dummy data DDT and the rise of external clock ECK delays by 1 ns to the rise of dummy data DDT, the phase comparison circuit 1 outputs the up clock UCK of, e.g. one clock to the counter 2.
In this case, the counter 2 supplies the count value CT of xe2x80x9c1xe2x80x9d, which is counted up according to the up clock UCK of one clock supplied from the phase comparison circuit 1, to the DAC 3. The DAC 3 converts the count value CT of xe2x80x9c1xe2x80x9d, which is supplied from the counter 2, into analogue delay voltage VD, 0.1 V in this case, and outputs it to the delay circuit 4. In the delay circuit 4, delay voltage VD of 0.1 V is applied to the gate of the FETs 15 to 17. Therefore, the source-to -drain conductance (reciprocal number of resistivity) of the FETs 15 to 17 increases according to the delay voltage VD of 0.1 V. So, since the connection point between the output of the inverter 11 and the input of the inverter 12 is connected with one end of the capacitor 18 based on the above value of conductance, the delay time of the unit delay circuit composed of the inverter 11, FET 15 and capacitor 18 becomes longer. Similarly, the delay time of the unit delay circuit composed of the inverter 12, FET 16 and capacitor 19, and the delay time of the unit delay circuit composed of the inverter 13, FET 17 and capacitor 20 also become longer. Therefore, the delay time of the entire delay circuit 4 becomes longer. Accordingly, the internal clock ICK is delayed more than before, thereby the phase of external clock ECK coincides with the phase of dummy data DDT. So, data can be output from the buffers 7 and 8 synchronizing with the phase of external clock ECK.
By this composition, read from the semiconductor device are data DT1 and DT2 to be synchronized with the internal clock ICK generated synchronizing with the external clock ECK.
Meanwhile, in the semiconductor device equipped with the conventional DLL, the output dummy circuit 9 corresponds to the pseudo-composition of FF, buffer or capacitance of load connected to the output terminal that compose the output circuit. However, in a case that the output terminal is connected to a lead terminal, or in a case that there occurs parasitically an inductive load because of the semiconductor device being encapsulated in a package, or in a case that there occurs parasitically a capacitive load because of the semiconductor device being mounted on a printed board and soldered onto its pattern, since the load varies depending on the characteristics of package or the mounting conditions, it is impossible to make the output dummy circuit 9 with the same characteristic as the output circuit that actually outputs data while considering all of the conditions. Especially the inductance cannot be made even by using the current technology of semiconductor device.
Thus, even if the phase of dummy data DDT to be output from the output dummy circuit 9 that does not have the same characteristic as the output circuit that actually outputs data is made to correspond to the phase of external clock ECK, data DT1 and DT2 actually output from the output circuit are, as shown in FIG. 3, not capable of being synchronized with the external clock ECK. Accordingly, especially in synchronous semiconductor storage, since data read from that may not be synchronized with the external clock ECK, the PCU fails to accurately read data, therefore the CPU and the entire system will be subjected to a malfunction.
Also, in the semiconductor device equipped with the conventional DLL, since the output dummy circuit 9 composing the DLL always operates, the power consumption of the output dummy circuit 9 is much more than that of other circuit elements composing the semiconductor device, therefore it is not negligible. Namely, the delay circuit and the output dummy circuit 9 are, in general, composed of multiple inverters cascade-connected, and the circuit current flows every time the inverter conducts the operation of inversion.
In addition, since semiconductor devices rapidly increase in operating speed, a clock or dummy pattern to pass through the delay circuit and the output dummy circuit 9 is correspondingly apt to increase in frequency. Thus, since the number of inversion operation in the inverter increases as the frequency of clock etc. becomes higher, the power consumption of the delay circuit 4 and the output dummy circuit 9 also increases.
Furthermore, in general the phase difference between dummy data DDT and external clock ECK varies depending on the surrounding temperature of semiconductor device. When the output dummy circuit 9 consumes power as much as described above, it generates heat necessarily. Therefore, the heat generated may adversely affect the delay locked operation. In other words, the operation of the output dummy circuit 9 that is installed, essentially, to remove the phase difference causes a reversed phenomenon that the phase difference is widened.
Also, the output dummy circuit 9 described above is not directly related to the essential function of the semiconductor device and does not contribute to accurate delay locked operation. Despite these, it has a big occupied area in the chip. Therefore, it causes a problem that the chip size increases by that much.
Accordingly, it is an object of the invention to provide a synchronizing method for delay locked loop, a delay locked loop, and a semiconductor device equipped with the delay locked loop that accurate delay locked operation can be conducted with low power consumption and a smaller chip size.
According to the invention, a synchronizing method for delay locked loop, comprises the step of:
conducting the delay locked operation that makes the phase of external clock ECK being supplied from outside coincide with the phase of data being output outside synchronizing with internal clock ICK that is delayed by a given delay time from the external clock ECK by changing the delay time, thereby generating the internal clock ICK synchronized with the external clock ECK;
wherein the delay locked operation is conducted only when a command or signal is supplied from outside, and the delay time changed previously is retained when the command or signal is not supplied.
According to another aspect of the invention, a delay locked loop, comprises:
a delay circuit that outputs internal clock ICK being delayed by a given delay time from external clock ECK supplied from outside;
an output circuit that outputs data being synchronized with the internal clock ICK to outside;
a phase comparison circuit that compares the phase of output data of the output circuit with the phase of the external clock ECK; and
a delay time changing means for changing the delay time according to the phase comparison result of the phase comparison circuit;
wherein the delay locked loop conducts the delay locked operation to generate the internal clock ICK being synchronized with the external clock ECK only when a command or signal is supplied from outside, and the delay time changing means retains the delay time changed previously when the command or signal is not supplied.
According to another aspect of the invention, a semiconductor device, comprises,
a delay locked loop that comprises:
a delay circuit that outputs internal clock ICK being delayed by a given delay time from external clock ECK supplied from outside;
an output circuit that outputs data being synchronized with the internal clock ICK to outside;
a phase comparison circuit that compares the phase of output data of the output circuit with the phase of the external clock ECK; and
a delay time changing means for changing the delay time according to the phase comparison result of the phase comparison circuit;
wherein the delay locked loop conducts the delay locked operation to generate the internal clock ICK being synchronized with the external clock ECK only when a command or signal is supplied from outside, and the delay time changing means retains the delay time changed previously when the command or signal is not supplied.
According to another aspect of the invention, a semiconductor device, comprises:
a delay circuit that outputs internal clock ICK being delayed by a given delay time from external clock ECK supplied from outside;
a plurality of output circuits that output a plurality of data being synchronized with the internal clock ICK to outside;
a phase comparison circuit that compares the phase of a dummy pattern that is supplied to and output from any one of the plurality of output circuits, the dummy pattern being formed so that xe2x80x9cHxe2x80x9d level and xe2x80x9cLxe2x80x9d level are repeated at a given cycle and a given ratio, with the phase of the external clock ECK; and
a delay time changing means for changing the delay time according to the phase comparison result of the phase comparison circuit;
wherein the delay locked operation to generate the internal clock ICK being synchronized with the external clock ECK is conducted only when a command or signal is supplied from outside, and when the command or signal is not supplied, the delay time changing means retains the delay time changed previously and the output circuit subjected to the supply of the dummy pattern outputs the data being synchronized with the internal clock ICK to outside.